1. Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuits and, more particularly, to an improved process for fabricating high-voltage devices. According to the present invention, the salicide process is integrated with the high-voltage process, thereby reducing the resistance of high-voltage metal-oxide-semiconductor transistor devices.
2. Description of the Prior Art
Integrated circuits (ICs) containing both high-voltage and low-voltage devices such as high/low voltage MOS transistor devices are known in the art. For example, the low-voltage device may be used in the control circuits as the high-voltage device may be used in electrically programmable read only memory (EPROM) or the driving circuits of the liquid crystal display devices.
It is also known that self-aligned silicide (also referred to as “salicide”) process is typically utilized to form metal silicide layer such as cobalt silicide or titanium silicide on the gates, source or drain regions in order to reduce sheet resistances. However, the salicide process is merely performed on the low-voltage devices. Considering hot carrier effects, the conventional high-voltage process cannot integrate with the salicide process. As a result, the sheet resistance of the high-voltage devices is high.
In light of the above, there is a need to provide an improved method for reducing the sheet resistance of the high-voltage devices.